Insulated gate bipolar transistors (IGBTs) are popular control devices for automobile ignition systems. The IGBT can carry large currents with very low resistance and can be rapidly switched on and off with a low voltage gate. They combine the control characteristics of DMOS devices with the current carrying capacity of thyristor.
A typical IGBT is shown in FIG. 4a. Those skilled in the art understand that some IGBTs are formed in striped cellular arrays of bases with sources. As shown in FIG. 4a, the IGBT 10 has an epitaxial layer 11 that includes two N+ source stripes regions 2a, 2b surrounded by P-typed base stripe regions 3. The portion 3a of the base 3 that lies between the source stripes is designated as the body stripe. The epitaxial layer 11 has a lightly doped N drift region 5 over a heavily doped N buffer region 7. The epitaxial layer 11 is formed on top of a heavily P doped substrate 9. On top of the device, gate insulating stripes 17, typically of silicon dioxide, cover the top of the epitaxial layer 11. Gate conductive stripes 19, typically polysilicon 19, cover the insulating stripes 17 and form a gate electrode. The gate overlies channel stripes 30a, 30b on opposite sides of the base stripe 3. Another insulating layer 21 covers the polysilicon stripes 19 and a metal contact stripe 23 contacts the source stripes 2a, 2b, N+ source contact regions 20 and the body stripe 3a of each cell. The above description is for a planar device with the gate on the surface. However, the IGBT may be fabricated with a trench gate. See FIG. 4b. 
IGBTs may be used in ignition control circuits such as those shown in FIGS. 1 and 2. Those circuits are discussed in this Background portion of the specification in order to explain the invention. The location of that discussion and the discussion itself are not admissions that the circuits are prior art. When the IGBT 10 is on, it drops a low voltage VCE(sat) and current flows through the primary side 12 of transformer 14. The ratio of the primary to the secondary coil 16 is about 100:1. The voltage is allowed to build to about 400 volts across the primary. When the spark plug is triggered, most of the energy is discharged in the spark. If there is any residual energy, it is dissipated by an auxiliary clamp circuit 80. In FIG. 1 the clamp circuit 80a is a single pair or multiple pairs of Zener diodes 82, 84 with a cumulative breakdown voltage of about 400 volts. In FIG. 2 the clamp circuit 80b is a voltage divider including resistors R1, R2 and a single pair or multiple pairs Zener diodes 86. After the gate signal is removed, auxiliary circuits 80 keep the IGBT 10 on in order to dissipate residual energy and prevent a localized failure.
The voltage for the auxiliary circuits 80 is set by the zener diodes to dissipate the energy over time. A problem arises if there is no spark due to, for example, a broken spark plug wire or a fouled plug. That leaves an open secondary 16 and the energy remains stored in the inductors 12, 16. With the gate turned off, the energy stored in the primary 12 cannot be transferred to the secondary 16. The primary 12 forces the voltage to rise until the zeners break down. In the self clamped inductive switching (SCIS) mode a portion of the collector current, Izener, is diverted from the collector and into the gate to keep the IGBT on. Then energy stored in the primary inductor 12 will dissipate even after the gate signal is removed.
In the SCIS mode the IGBT must absorb all the energy stored in the ignition coil during abnormal operating conditions. The most common abnormal condition is an open secondary. The silicon area of the IGBT is defined by its SCIS energy density capability. Therefore, it is imperative that the SCIS energy density (mJ/cm2) be increased because shrinking the silicon area reduces cost and the IGBT footprint is reduced to free up module space. A 60% reduction in the footprint can be realized by offering the same SCIS capability in the DPak (TO-252) rather than a D2Pak (TO-263). Supplying the same device performance in a DPak allows the module designer to add this functionality without increasing the module size.
In the clamping phase of the SCIS mode, a portion of the collector current is fed back to the gate after the diodes in FIGS. 1 and 2 avalanche. This current develops the required gate plateau voltage VGE(plateau) across the RGE or R2 to deliver the necessary p-n-p base electron current required to conduct the total decaying current from the energy stored in the primary coil at the clamping voltage. See FIG. 3. The VGE(plateau) continually self adjusts because it is a function of the IGBT threshold voltage (Vth), p-n-p current gain (xcex1p-n-p), Pbase leakage current, and channel mobility (xcexcns). All of the above are a function of the device temperature. So VGE(plateau) decreases with temperature because of the following factors:
1. The Vth voltage has a negative temperature coefficient.
2. The xcex1p-n-p has a positive temperature coefficient, reducing the percentage of electron current to deliver the total decaying SCIS current.
3. The electron current generated from the Pbase leakage current has a positive temperature coefficient. Refer to stripe cell cross-section shown in FIG. 4. This reduces the amount of electron current required to drift across the channel because the leakage current can supply part of the p-n-p base current.
VGE(plateau) increases with temperature because the degradation in xcexcns with increasing temperature causes a de-biasing effect.
Factors 1, 2, and 3 outweigh factor 4. So as the device 10 heats up and current decays VGE (plateau) will decrease at an accelerated rate. If VGE (plateau) reaches zero anywhere on the die while the temperature is still rising and an appreciable amount of current ( greater than 1A) is still decaying from the primary to induce localized thermal runaway, the device will fail to maintain the clamping function and may fail destructively. As such, it is desirable to find a solution for keeping VGE(plateau) high during SCIS clamping.
Others have tried to extend the SCIS capability by decreasing the cell pitch to more uniformly distribute the heating during SCIS by reducing the localized current density. In some designs the cell is full channel and N+ channel doping is contacted along the entire length of the stripe as showed in FIG. 5. With such designs, VGE (plateau) during SCIS is reduced because the electron current density per unit channel width is reduced. Thus, such designs fail to improve SCIS performance. Another design to improve SCIS performance relies upon dividing the channel width into multiple segments as shown in FIG. 6. The channel width is reduced by excluding the N+ channel doping. This can be accomplished by a simple lithographic bar pattern with the results shown in the bottom half of FIG. 6. The N+ doping need not be continuous across the contact opening as shown in the top half of FIG. 6. The segments of the channel can be connected in their centers or at their ends. See the versions showed in FIGS. 7 and 8. In both figures, contact is made again along the full length of the N+ channel doping. The N+ contact areas are not required, nor must they be continuous across the contact opening. These methods increase VGE(plateau) and the electron current density per unit channel width. The higher electron current per unit channel width increases the maximum peak temperature before all the IGBT p-n-p base current can be supplied by the increasing Pbase leakage current.
The invention improves SCIS performance by altering the structure of the source contact regions and by altering the structure of the sources. In particular, channel resistances are added to the device in order to more effectively distribute the heat across the surface of the die. The construction of the IGBT is altered so that contact to the source stripes is made only substantially through the source contact regions. As such, prior art techniques that relied upon contacting the source stripes along their entire length are not used. The portion of the source stripe adjacent the body region is either excluded from doping or is suitably shielded by an insulating layer. The invention also divides source stripes along the width of the channel into a plurality of segments. These segments may be of equal length and opposite each other and connected at their middles by a source contact region. In another embodiment the source stripe segments may be jogged with respect to each other so that the source contact region connects the head of one segment to the tail of another segment on the opposite side of the body stripe.
The invention provides an insulated bipolar transistor device (IGBT) that has a substrate heavily doped with a first dopant of one polarity, conventionally P-type doping. Above the substrate are buffer and drift layers typically comprising N-type dopants. The buffer layer is heavily doped and adjacent the substrate. The drift layer is more lightly doped and extends to the surface of the device. The surface of the device has a number of elongated base stripe regions formed with P-type dopants. Each base stripe region is bordered by the drift layer and extends along a length of the surface. The IGBT has numerous base stripes. Within each of the base stripes there are first and second source stripes. The source stripes are typically formed with N-type dopants and are located opposite each other and near the edges of their base stripe. The source stripes are essentially parallel to each other and extend in the same direction as the base stripes. A region in the base stripe and between the source stripes define a body stripe of P-type dopant. Portions of the base stripe between the source stripes and the proximate bordering drift layer define channel regions for the IGBT. A gate electrode is over each channel. The gate electrodes include gate oxide stripe, a conductive gate stripe and an insulating layer over the conductive gate stripe. A source contact layer, typically of metal, extends through vias in the insulating layer. The vias are at a number of locations aligned with the polysilicon gate and body stripe. The source contact layer fills the vias in the insulating layer and makes contact to a number of source contact regions. The source contact regions are typically heavily N-doped and are disposed in the body stripe. The source contact regions extend from the body stripe to one or both of the source stripes and are in electrical contact with the source contact layer. The insulating layer covers the portions of the source stripes that are proximate the body regions. Thus, the only contact to the source stripes is through the source contact regions.
In one embodiment, the source stripes are continuous and are periodically interconnected by source contact regions. The source contact regions and the source stripes may have the same heavy N-type doping. As an alternative, their stripes may have less of an N-type doping concentration. The invention also divides the source stripes into a plurality of elongated source segments comprising head and tail sections and elongated bodies. The source segments are spaced from each other along opposite sides of the body stripe. Portions of the body region extend between sequential head and tail sections of the segments in order to separate the sequential source stripe segments from each other. In one embodiment the source segments are the same length and are connected together at approximately the middle of their lengths by an source contact region. In another embodiment, the source stripes on either side of the body region are jogged with respect to each other. In that embodiment, the head of a source stripe on one side of the body stripe is connected across the body to the tail of another source stripe on the opposite side of the body stripe by a source contact region.